Semiconductor memory device, refresh control method thereof, and test method thereof

ABSTRACT

The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a refresh control method of asemiconductor memory device, and particularly to a reduction in currentconsumption in a standby state.

[0003] 2. Description of the Related Art

[0004] A semiconductor memory device requiring a refresh operation mustperform a refresh operation on a regular basis even in a standby statein which a low current consumption operation is required. A reduction incurrent consumption at the refresh operation is essential.

[0005] In memory cells installed in a semiconductor memory device ingeneral, each of characteristics for holding data stored therein hassome width. Therefore, a refresh cycle tREF equivalent to a timeinterval in which the same memory cells are refreshed, must be set to avalue worst in data-holding characteristics. However, it is enough formemory cells each having more excellent data-holding characteristics ifthe refresh operation is performed in a cycle longer than the setrefresh cycle tREF. Therefore, there has been proposed a so-calledrefresh-thinning-out operation in which one refresh operation iseffected on each of memory cells each having satisfactory data-holdingcharacteristics every 2 cycles or more of the refresh cycle tREF. Thus,the number of refresh operations per predetermined time can be reducedand current consumption at the refresh operation can be reduced.

[0006] A semiconductor memory device having a refresh-thinning-outfunction has been disclosed in Japanese Laid-Open Patent publication No.9-102193. FIG. 24 mainly shows a circuit configuration of a row addresssystem. The same figure shows, as an example, a case in which a/CASbefore/RAS (hereinafter abbreviated as “CBR”) refresh operation isprovided with a refresh-thinning-out function.

[0007] A timing circuit 131 outputs a trigger signal corresponding to anactivation signal φR for activating a row address decoder 137 withpredetermined timing according to a control signal supplied to a controlterminal 101. This trigger signal is inputted to an AND logic gate 400b. Further, the timing circuit 131 outputs an activation signal 41 foractivating a refresh-thinning-out control circuit 105 to be describedlater.

[0008] A row address buffer 132 latches an address signal supplied toaddress terminal 101 at a fall time of a control signal /RAS andsupplies the latched address signal to an address selector 135 as rowaddress Add(O).

[0009] A CBR judgment circuit 133 outputs a refresh command signal φCBRaccording to the execution of the setting of a CBR refresh mode.

[0010] A CBR counter 134 counts the falling edge of the refresh commandsignal φCBR and outputs refresh address Add(C) to an address selector135.

[0011] The address selector 135 is controlled by the refresh commandsignal φCBR to couple or link the row address buffer 132 and the rowaddress decoder 137 upon read and write operations and couple the CBRcounter 134 and the row address decoder 137 upon the refresh operation.

[0012] The refresh-thinning-out control circuit 105 activated by theactivation signal φ1 is inputted with the refresh address Add(C)outputted from the CBR counter 134 and judges whether the address Add(C)is a registered address. The refresh-thinning-out control circuit 105outputs a refresh permission signal φ2 to the other input terminal ofthe AND logic gate 400 b according to the result of judgment to controlthe output of the activation signal φR.

[0013] The row address decoder 137 is activated by the activation signalφR to thereby allow a word driver 104 to activate any one of a pluralityof word lines (WL0 through WLn) in a memory-cell array 140 according tothe row address Add(O) or refresh address Add(C) inputted via theaddress selector 135.

[0014] Namely, since a control signal /RAS falls ahead of a controlsignal /CAS in a normal write/read cycle, an output signal φCBR of theCBR judgment circuit 133 is held at a deactivation level. Therefore, theaddress selector 135 outputs row address Add(O) outputted from the rowaddress buffer 132 to the row address decoder 137. Thereafter, the rowaddress decoder 137 is activated by an activation signal φR produced bythe timing circuit 131 to thereby activate the corresponding word linecorresponding to the write/read cycle.

[0015] Since the control signal /CAS falls ahead of the control signal/RAS in a CBR refresh cycle, the output signal φCBR of the CBR judgmentcircuit 133 is brought to an activation level. Therefore, the addressselector 135 outputs refresh address Add(C) outputted from the CBRcounter 134 to the row address decoder 137. When the refresh addressAdd(C) and its corresponding registered address coincide with each otherat this time, a permission signal φ2 is activated and an activationsignal φR is supplied to the row address decoder 137, so that a wordline corresponding to the refresh address Add(C) is activated. When theyare found not to coincide with each other, the activation signal φR ismasked so that no word line is activated.

[0016]FIG. 25 shows a circuit diagram of the refresh-thinning-outcontrol circuit 105 with being taken as the center. n+1 bit internaladdress signals A0′-An′, and their inverted signals /A0′-/An′, whichconstitute refresh address Add(C) outputted from a CBR counter 134, areinputted to address registration circuits 1.1-1.r.

[0017] The address registration circuits 1.1-1.r are respectivelyprovided with an NMOS transistor 600, and fuses 7.0-7.n and NMOStransistors 8.0-8.n, and fuses 7.0′-7.n′ and NMOS transistors 8.0′-8.n′respectively provided in association with the address signals A0′-An′and their inverted signals /A0′-/An′.

[0018] When the refresh address Add(C) coincides with any of addressesregistered in the address registration circuits 1.1-1.r, a signalcorresponding to any of outputs φH1-φHr of the address registrationcircuits 1.1-1.r is brought to a high level, and hence a refreshpermission signal φ2 is rendered high in level.

[0019] As a result of an increase in the function required for aportable device with the popularization thereof, there has recently beena further demand for a large-capacity memory as an alternative to theconventionally-mounted static random access memory (hereinafter called“SRAM”). Since it is necessary to package or mount the memory in alimited space at the actual price, a refresh-function built-in DRAM socalled pseudo SRRAM, having built in control related to a refreshoperation peculiar to a memory cell such as a DRAM has been used whileeach memory cell for a dynamic random access memory (hereinafter called“DRAM”) formed in high integration and low in bit unit price is beingused as an alternative to each memory cell of the SRAM. Thus, anexternal controller controls the operation for performing a self-refreshcommand or for conducting self-refresh operation during an externalaccess-free period then, pseudo SRAM has been equipped with a so-calledself-refresh mode in which control or the like on each refresh addressis preformed. In reply to a future's high-speed demand, specs of aso-called pseudo SSRAM adapted to external specs of a synchronous SRAM(hereinafter called “SSRAM”) are becoming a reality.

[0020] However, the semiconductor memory device having therefresh-thinning-out function, which has been illustrated in JapaneseLaid-open Patent Publication No. 9-102193, needs to register rowaddresses requiring the execution of refresh every refresh cycle tREFthrough the use of the address registration circuits 1.1-1.r andrequires the address registration circuits 1.1-1.r every row address.Further, the respective address registration circuits 1.1-1.rrespectively need fuses corresponding to bit widths of the row address.Namely, the total number of fuses to be mounted to the semiconductormemory device needs (bit widths of row address)×(number of row addressesto perform refresh every cycle). In order to obtain an effectivereduction effect of current consumption by the refresh operation withrespect to the distribution of data-holding characteristics in thesemiconductor memory device, a large number of fuses must be providedand an increase in die size of the semiconductor memory device might beincurred, thus resulting in a problem.

[0021] Since a large number of fuses are cut when the correspondingaddresses are registered in the address registration circuits 1.1-1.r,much test time is needed. It is further assumed that since the refreshaddress Add(C) is generated by the built-in counter, external control isrestricted, and much test time is required upon execution of afunctional test even in the case of, for example, the setting ofrefresh-thinning-out control on each redundant region for substituting acharacteristic defective cell with another, thus causing a problem.

[0022] Since the refresh address Add(C) is connected even to therefresh-thinning-out control circuit 105 as well as to the row addressbuffer 137, the CBR counter 134 must drive these loads, thus being indanger of causing an increase in drive current. Since therefresh-thinning-out control circuit 105 takes such a configuration asto always make a comparison between the refresh address Add(C) and eachregistered address regardless of judgment as to execution/non-executionof the refresh operation, unnecessary currents consumed will flow evenduring a judgment operation-free period. A problem arises in that thisis danger of being unable to meet the demand for low current consumptiondue to these currents consumed. Since the current consumption isoriginally low upon standby in particular, the rate of an operatingcurrent of the refresh-thinning-out control circuit 105 to the totalcurrent consumption becomes large, thus resulting in a problem for thereduction in current consumption.

[0023] While the load on the external controller for the refreshoperation has heretofore been significantly lightened in thesemiconductor memory device called the pseudo SRAM or pseudo SSRAM,there is still a need to perform its control by the external controller.There may be a case in which it is necessary to provide a dedicatedcontrol terminal upon its control. Therefore, it is hard to say that theconventional pseudo SRAM or the like has the perfect compatibility withan SRAM or SSRAM in which such control or a dedicated control terminalis unnecessary. To this end, there has been proposed a semiconductormemory device having such specs that in order to bring the compatibilitynear to the perfect one, a refresh operation and a normal read/writeoperation are executed independently of each other with occasionaltiming while the refresh operation is being incorporated therein as aninternal access operation. However, the semiconductor memory device isaccompanied by a problem that when a refresh-thinning-out function isadded thereto, a refresh operating time might be long due to the timerequired to make a decision as to refresh address by arefresh-thinning-out control, and a delay in propagation due to a loadimposed on the refresh address on a signal path, thus causing apossibility that an operational cycle time will become long.

SUMMARY OF THE INVENTION

[0024] The present invention has been made to solve at least one of theproblems of the prior art. It is therefore a main object of the presentinvention to provide a semiconductor memory device which is capable ofachieving a further reduction in current consumption insufficient forthe conventional semiconductor memory device and is free of incurring ofan operational increase in delay even if applied to a pseudo SRAM or thelike having high compatibility and which is capable of realizing asuitable refresh-thinning-out function to thereby reduce currentconsumption in a standby state, and a refresh control method of thesemiconductor memory device.

[0025] In order to achieve the above object, a semiconductor memorydevice according to a first aspect of the present invention comprises,when target word lines are sequentially selected according to refreshrequest signals to thereby perform refresh operations, a designatorsection for designating a corresponding address group related to a wordline group to be intended for the refresh operation, based on aplurality of the refresh request signals, a storage section for storingin advance a predetermined address group related to a predetermined wordline group including word lines connected with memory cells havingpredetermined data-holding characteristics, a comparator section forcomparing the corresponding address group designated by the designatorsection and the predetermined address group stored in the storagesection, and a judgment section for judging whether the refreshoperation is executable, according to the result of comparison.

[0026] In the semiconductor memory device according to the first aspectof the present invention, the comparator section compares thecorresponding address group designated by the designator section andrelated to the target word line group according to the plurality ofrefresh request signals, and the predetermined address group stored inthe storage section and related to the predetermined word line groupincluding the word lines connected with the memory cells each having thepredetermined data-holding characteristics. The judgment section judgeswhether the refresh operation for the corresponding address group isexecutable, according to the result of comparison.

[0027] Further, a refresh control method of the semiconductor memorydevice according to the first aspect of the present invention comprisesa step of sequentially selecting target word lines according to refreshrequest signals to thereby perform refresh operations, and a step ofjudging whether a refresh operation is executable, according todata-holding characteristics stored in each of memory cells connected toa word line group, for each corresponding address group related to aword line group to be intended for the refresh operation in response toa plurality of refresh request signals.

[0028] Thus, a fuse, a ROM, a RAM and the like provided to be stored inthe storage section may be provided for each corresponding addressgroup. As compared with the case in which they are provided everyaddresses related to target word lines according to refresh requestsignals, the exclusively possessed area of the storage section to a diesize of a semiconductor memory device can be reduced.

[0029] Since the units of judgment as to execution/non-execution of therefresh operations are collected up for each corresponding addressgroup, the refresh-operation execution judgment might be made inclusiveof word lines each free of the need for execution of the refreshoperation. Upon the setting of making a decision as to itsexecution/non-execution for each individual word line in reverse, thereis a need to provide storage sections every addresses related to theword lines, and hence the exclusively possessed area of each storagesection will increase. Namely, the exclusively possessed area of thestorage section and a reduction in current consumption byrefresh-thinning-out has a contradictory relationship. By adjusting thenumber of occurrences of refresh request signals collected up with thecorresponding address group, the reduction in current consumption by therefresh-thinning-out operation can be realized while the increase in theexclusively possessed area of the storage section is being suppressed.

[0030] A semiconductor memory device according to a second aspect of thepresent invention comprises, when target word lines are sequentiallyselected according to refresh request signals to thereby perform refreshoperations, a refresh-thinning-out controller section including adesignator section for designating a corresponding address related to aword line intended for the refresh operation according to each of therefresh request signals, and a judgment section for comparing eachcorresponding address and a predetermined address related to apredetermined word line connected with one of memory cells each havingpredetermined data-holding characteristics and judging whether therefresh operation is executable, according to the result of comparison,and a switching section for switching an active state of therefresh-thinning-out controller section under predetermined conditions,wherein when the refresh-thinning-out controller section isdefunctionalized, the switching section deactivates at least either oneof the designator section or the judgment section.

[0031] Thus, since at least either the designator section or thejudgment section is deactivated where no refresh-thinning-out operationis carried out, current consumption due to an unnecessary circuitoperation can be reduced.

[0032] A semiconductor memory device according to a third aspect of thepresent invention comprises, when target word lines are sequentiallyselected according to refresh request signals to thereby perform refreshoperations, a storage section for storing each of predeterminedaddresses each compared with a corresponding address related to eachword line intended for the refresh operation, a storage switchingsection for switching each of the predetermined addresses to be storedin the storage section between addresses at which memory cells eachhaving first data-holding characteristics are included, and addresses atwhich memory cells each having second data-holding characteristics areincluded, according to a distribution of data-holding characteristicsincluded in memory cells, and a judgment section for switching theresult of judgment as to execution/non-execution of the refreshoperation according to the switching of the storage switching section.

[0033] In the semiconductor memory device according to the third aspectof the present invention, the storage switching section switches each ofthe predetermined addresses to be stored in the storage section betweenthe addresses including the memory cells having their data-holdingcharacteristics corresponding to the first and second data-holdingcharacteristics according to the distribution of the data-holdingcharacteristics of the memory cells in the semiconductor memory device,and performs switching to the result of judgment as toexecution/non-execution made by the judgment section.

[0034] Thus, since each of the predetermined addresses to be stored inthe storage section is switched according to the distribution of thedata-holding characteristics stored in the memory cells in thesemiconductor memory device and the switching to the result of judgmentas to the execution/non-execution of the refresh operation can beperformed. Therefore, the predetermined addresses can be switchedaccording to the distribution of the data-holding characteristics sothat the number of predetermined addresses to be stored in the storagesection is reduced. The layout number of fuses, ROMs, RAMs or the liketo be provided for the storage section is compressed to make it possibleto suppress an increase in the die size of the semiconductor memorydevice.

[0035] Since the number of the predetermined addresses to be stored iscompressed, the procedure of storing the predetermined addresses to thestorage section can be lightened. The shortening of a processing timeand a reduction in processing cost with its shortening can be achieved.

[0036] Here, a refresh cycle tREF is determined according to the abilityof data-holding characteristics of each memory cell. Namely, there is aneed to effect a refresh operation on each memory cell relatively poorin data-holding characteristics in a shorter period of time. Since therefresh cycle tREF is set under rate-control to each memory cell poor indata-holding characteristics, a decision as to theexecution/non-execution of the refresh operation is made to each memorycell relatively good in data-holding characteristics according to eachof refresh request signals, and the refresh operation may be effectedthereon as needed. On the other hand, there is a need to effect therefresh operation on each memory cell relatively poor in data-holdingcharacteristics for each refresh request signal.

[0037] A semiconductor memory device according to a fourth aspect of thepresent invention comprises a refresh-thinning-out controller sectionfor comparing a corresponding address related to each of the target wordlines and each of predetermined addresses related to predetermined wordlines connected with memory cells each having predetermined data-holdingcharacteristics and judging whether the refresh operation is executable,according to the result of comparison, and an output section activatedupon testing and for outputting the result of judgment from therefresh-thinning-out controller section to the outside.

[0038] In the semiconductor memory device according to the fourth aspectof the present invention, the output section is activated upon testingto output the result of judgment sent from the refresh-thinning-outcontroller section to the outside.

[0039] Thus, the result of judgment as to the execution/non-execution ofthe refresh operation by the refresh-thinning-out controller section canbe observed externally as needed. It can be made available for a failanalysis, a characteristic examination and the like of the semiconductormemory device, and a characteristic test can be executed efficiently.

[0040] A semiconductor memory device according to a fifth aspect of thepresent invention comprises a refresh-thinning-out controller sectionfor comparing each of corresponding addresses related to each of thetarget word lines and each of predetermined addresses related topredetermined word lines connected with memory cells each havingpredetermined data-holding characteristics and judging whether therefresh operation is executable, according to the result of comparison,and redundant memory cells for relieving defective memory cells, whereinof the corresponding addresses, redundant addresses in which redundancysetting for the redundant memory cells has been performed, are notjudged by the refresh-thinning-out controller section.

[0041] In the semiconductor memory device according to the fifth aspectof the present invention, when the corresponding addresses areredundancy-set to their corresponding redundant addresses to relieve thedefective memory cells by the redundant memory cells, the redundantaddresses are not judged by the refresh-thinning-out controller section.

[0042] A refresh control method of the semiconductor memory deviceaccording to the fifth aspect of the present invention comprises a stepof sequentially selecting target word lines according to refresh requestsignals to thereby perform refresh operations, and a step of avoidingjudgment as to execution/non-execution of the refresh operation withrespect to redundant addresses subject to redundancy setting, ofcorresponding addresses related to the target word lines.

[0043] Thus, since the judgment as to the execution/non-execution of therefresh operations is not effected on the redundancy-set redundantmemory cells, the test of measuring data-holding characteristics foreach of the redundant memory cells and selecting a predetermined addressfor performing refresh-thinning-out control, from within redundantaddresses as needed becomes unnecessary. An increase in test time can besuppressed.

[0044] A semiconductor memory device according to a sixth aspect of thepresent invention, wherein an external access operation executed basedon each of external-access request signals and a refresh operationexecuted based on each of refresh request signals produced automaticallythereinside are executed independently of each other, comprises anarbiter section for making arbitration to the external-access requestsignal and the refresh request signal, a controller section forcontrolling decode processing of each corresponding address with respectto either the external access operation or the refresh operationdetermined by the arbiter section, a word line driver section fordriving a row address decoder for the corresponding address, which isstarted up by the controller section, and each word line selected by therow address decoder; and a refresh-thinning-out controller section formaking a decision as to execution/non-execution of the refresh operationwith respect to the corresponding address outputted according to therefresh request signal, wherein the row address decoder or the word linedriver section is activated and controlled based on the result ofdetermination by the refresh-thinning-out controller section.

[0045] In the semiconductor memory device according to the sixth aspectof the present invention, the arbiter section arbitrates theexternal-access request signal and the refresh request signal to therebydetermine either one of the external access operation and the refreshoperation. Next, the decode processing is started under control madefrom the controller section with respect to the determined operation.Thus, a series of operations from the decode processing of eachcorresponding address by the row address decoder to the driving processof each word line selected by the word line driver section are advancedor put forward. In parallel with this series of operations, therefresh-thinning-out controller section makes a refresh-operationexecution/non-execution decision as to each corresponding addressoutputted according to the corresponding refresh request signal andthereby activates and controls the row address decoder or the word linedriver section according to the result of decision referred to above.

[0046] A refresh control method of the semiconductor memory deviceaccording to the sixth aspect of the present invention comprises a stepof executing an external access operation based on each ofexternal-access request signals and a refresh operation based on each ofrefresh request signals produced automatically thereinside, the externaloperation and the refresh operation being executed independently of eachother, a step of selecting the refresh operation according toarbitration to the external-access request signal and the refreshrequest signal and performing a judgment process as toexecution/non-execution of the refresh operation relative to thecorresponding address in parallel with a word line driving process madefollowing a decode process of the corresponding address intended for therefresh operation, and a step of activating and controlling the decodeprocess or the word line driving process, based on the result ofjudgment as to the execution/non-execution thereof.

[0047] In the refresh control method of the semiconductor memory deviceaccording to the sixth aspect of the present invention, when the refreshoperation is selected according to the refresh request signal, theprocess of judging whether the refresh operation is executable, iscarried out in parallel with the decode process of the correspondingaddress and the word line driving process made following the decodeprocess. The decode process or the word line driving process isactivated and controlled according to the result of judgment.

[0048] Thus, since the process of judging whether the refresh operationis executable, is embedded in the time required for the process ofdecoding the corresponding address and for the word line drivingprocess, the time required to discriminate whether the refresh operationis executable, is not added to an operating time including the refreshoperation, so that an increase in operating time is avoided.

[0049] A semiconductor memory device according to a seventh aspect ofthe present invention, wherein an external access operation executedbased on each of external-access request signals and a refresh operationexecuted based on each of refresh request signals produced automaticallythereinside are executed independently of each other comprises anarbiter section for making arbitration to the external-access requestsignal and the refresh request signal, a refresh request section foroutputting the refresh request signal to the arbiter section, and arefresh-thinning-out controller section for making judgment as toexecution/non-execution of the refresh operation with respect to acorresponding address outputted according to the refresh request signal,wherein the refresh request section is controlled based on the result ofjudgment by the refresh-thinning-out controller section.

[0050] In the semiconductor memory device according to the seventhaspect of the present invention, the refresh-thinning-out controllersection judges whether the refresh operation is executable, with respectto each corresponding address outputted according to the refresh requestsignal and controls the refresh request section based on the result ofjudgment. When the refresh request signal is outputted from the refreshrequest section, the arbiter section makes arbitration between therefresh request signal and the external access request signal, so thateither one of the external access operation and the refresh operation isdetermined.

[0051] A refresh control method of the semiconductor memory deviceaccording to the seventh aspect of the present invention comprises astep of executing an external access operation based on each ofexternal-access request signals and a refresh operation based on each ofrefresh request signals produced automatically thereinside, the externaloperation and the refresh operation being executed independently of eachother, a step of judging whether the refresh operation is executable,with respect to each corresponding address outputted according to therefresh request signal, and a step of arbitrating the refresh requestsignal and the external-access request signal based on the result ofjudgment.

[0052] In the refresh control method of the semiconductor memory deviceaccording to the seventh aspect of the present invention, judgment as towhether the refresh operation is executable, is made to eachcorresponding address outputted according to the refresh request signal,and the refresh request signal is set as an arbitration signal, based onthe result of judgment, whereby an arbitration is made between therefresh request signal and the external-access request signal.

[0053] Thus, since the refresh request signal is not set as thearbitration signal at a stage prior to the judgment as to theexecution/non-execution of the refresh operation, the external accessoperation is immediately performed if the external-access request signalis produced during the process of judgment as to theexecution/non-execution thereof. The time required to discriminatewhether the refresh operation is executable, is not added as a delay inexternal access operation.

[0054] When judgment for prohibiting the refresh operation is made tothe refresh request signal, the refresh request signal is not madeavailable for arbitrations between the external-access request signaland the same. Namely, when the refresh operation is judged to beprohibited, the decode process of the corresponding address subsequentto the arbitrations between the request signals is not executed, andunnecessary circuit operations are stopped to make it possible to reducecurrent consumption.

[0055] A test method of a semiconductor memory device according toanother aspect of the present invention, wherein refresh operations areperformed according to judgment as to execution/non-execution of therefresh operations every refresh request signals while performingredundancy setting, comprises a redundant address acquiring step foracquiring each redundant address to be subjected to the redundancysetting, a predetermined address acquiring step for acquiringpredetermined addresses related to memory cells each havingpredetermined data-holding characteristics, and a storing step forstoring the redundant addresses and the predetermined addresses in thesemiconductor memory device in advance to exclude the two from an objectfor the judgment as to the execution/non-execution of the refreshoperation.

[0056] In the test method of the semiconductor memory device accordingto another aspect of the present invention, the redundant addressesacquired by the redundant address acquiring step are stored in thesemiconductor memory device in advance in addition to the predeterminedaddresses and excluded from the object for the judgment as to theexecution/non-execution of the refresh operation.

[0057] Thus, the predetermined addresses each having predetermineddata-holding characteristics and not subjected to the judgment as to theexecution/non-execution of the refresh operation, and the redundantaddresses can be both stored. The redundant addresses can be subjectedto settings free of the judgment as to whether the refresh operation isexecutable.

[0058] The test of measuring data-holding characteristics of a memorycell corresponding to each redundant address, and selecting apredetermined address for making refresh operationexecution/non-execution judgment, of the redundant addresses as needed,becomes unnecessary. An increase in test time can be suppressed.

[0059] The above and further objections and novel features of theinvention will more fully appear from the following detailed descriptionwhen the same is read in connection with the accompanying drawings. Itis to be expressly understood, however, that the drawings are for thepurpose of illustration only and are not intended as a definition of thelimits of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0060]FIG. 1 is a circuit block diagram of a semiconductor memory deviceaccording to a first embodiment;

[0061]FIG. 2 is a circuit block diagram illustrating an example of theinput of address to a refresh-thinning-out control circuit employed inthe first embodiment;

[0062]FIG. 3 is a layout diagram depicting an example of a layoutarrangement suitable for being equipped with a dedicated addressdecoder;

[0063]FIG. 4 is a circuit block diagram of a semiconductor memory deviceaccording to a second embodiment;

[0064]FIG. 5 is a circuit block diagram showing an example of the inputof address to a refresh-thinning-out control circuit employed in thesecond embodiment;

[0065]FIG. 6 is a layout diagram illustrating an example of a layoutarrangement suitable for provision with a buffer section for receivingpre-decode signal from a row pre-decoder;

[0066]FIG. 7 is an operation waveform diagram showing access competitionin a pseudo SRAM;

[0067]FIG. 8 is an operation waveform diagram of a burst length 1 in apseudo SSRAM (normal operation);

[0068]FIG. 9 is an operation waveform diagram of a burst length 1 in apseudo SSRAM (first embodiment—(1) and second embodiment);

[0069]FIG. 10 is an operation waveform diagram of a multi-burst lengthin the pseudo SSRAM (normal operation);

[0070]FIG. 11 is an operation waveform diagram of a multi-burst lengthin the pseudo SSRAM (first embodiment—(1) and second embodiment);

[0071]FIG. 12 is a circuit block diagram showing a refresh-thinning-outcontrol circuit (third embodiment);

[0072]FIG. 13 is a circuit block diagram illustrating a switchingsection employed in the third embodiment;

[0073]FIG. 14 is a circuit block diagram showing a dedicated addressdecoder employed in the third embodiment;

[0074]FIG. 15 is a circuit block diagram depicting a refresh-abilityrecorder section employed in the third embodiment;

[0075]FIG. 16 is a circuit block diagram showing a first judgmentsection employed in the third embodiment;

[0076]FIG. 17 is an operation waveform diagram illustrating operationsof the refresh-ability recorder section and the first judgment section;

[0077]FIG. 18 is a circuit block diagram depicting a second judgmentsection employed in the third embodiment;

[0078]FIG. 19 is an operation waveform diagram showing the operation ofthe second judgment section;

[0079]FIG. 20 is a circuit block diagram illustrating arefresh-thinning-out circuit equipped with a test facilitating function(fourth embodiment);

[0080]FIG. 21 is a flow chart showing a first specific example ofrefresh-thinning-out control circuit (fifth embodiment) in a redundantregion;

[0081]FIG. 22 is a circuit block diagram illustrating a second specificexample of the refresh-thinning-out control circuit (fifth embodiment)in the redundant region;

[0082]FIG. 23 is a layout conceptual diagram depicting column redundantconfigurations divided into blocks as viewed in a row address direction;

[0083]FIG. 24 is a circuit block diagram of a semiconductor memorydevice illustrative of a prior art; and

[0084]FIG. 25 is a circuit block diagram showing a refresh-thinning-outcontrol circuit employed in the prior art as the center.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0085] First through fifth embodiments illustrative of embodied ones ofa semiconductor memory device of the present invention and a refreshcontrol method of the semiconductor memory device will hereinafter bedescribed in detail based on FIGS. 1 through 23 while referring to thesedrawings.

[0086] The first embodiment shown in FIG. 1 shows a semiconductor memorydevice wherein a refresh-thinning-out function is added to operationspecs in which a built-in refresh operation and an external accessoperation are activated independently of each other with occasionaltimings. The present embodiment is a semiconductor memory device whereinsince the refresh operation and the external access operation can beperformed independently of each other, an external controller used forthe refresh operation becomes unnecessary, and a refresh-thinning-outfunction is provided after compatibility of a pseudo SRAM or a pseudoSSRAM to an SRAM or an SSRAM has been made more complete, whereby even areduction in current consumption at standby can be achieved.Incidentally, FIG. 1 shows only a section related to a rowaddress-system.

[0087] A predetermined control terminal 101 is connected to an I/Ocontroller section 13, which outputs an external-access request signalREQ(O) in response to a control signal inputted from the controlterminal 101. Together with address signals inputted from addressterminals 101 with a predetermined number of bits, the external-accessrequest signal REQ(O) is connected to a row address buffer 11, whichoutputs row address Add(O) to a row pre-decoder 102.

[0088] A refresh trigger signal RFTG outputted from a built-in refreshtiming timer section 14 for each predetermined time is inputted to arefresh address counter 12 and a refresh controller section 15 fromwhich a refresh request signal REQ(I) is outputted (in the case of acontrol method (2) to be described later). In the case of a controlmethod (1) to be described later, the refresh trigger signal RFTG servesas the refresh request signal REQ(I). The refresh address counter 12inputs refresh address Add(C) to the row pre-decoder 102 and inputspredetermined high-order bits of the refresh address Add(C) to arefresh-thinning-out control circuit 1 as high-order refresh addressAdd(C) (m).

[0089] The external-access request signal REQ(O) outputted from the I/Ocontroller section 13 and the refresh trigger signal RFTG (in the caseof the control method (1) to be described later) or the refresh requestsignal REQ(I) are inputted to an access arbiter 16. The access arbiter16 detects level transitions of the request signals each inputted as alevel signal or a pulse signal, thereby being capable of detecting asignal front and end between the request signals. When the pulse signalis needed, the provision of a circuit for generating a pulse signal withthe signal transition of the refresh signal RFTG as an edge is capableof coping with it (in the case of the control method (1)). In this case,the refresh controller section 15 is set to such a configuration as tooutput the pulse signal. A signal outputted from the access arbiter 16is inputted to a row-system controller section 17, which in turn outputscontrol signals CTL1 and CTL2 to the row pre-decoder 102, a main rowdecoder 103 and a word driver 18. Here, the main row decoder 103 isinputted with pre-decode signal AD(1) outputted from the row pre-decoder102 and selects a word line to be driven by the word driver 18, of wordlines WL0 through WLn disposed in a memory-cell array 140.

[0090] The refresh-thinning-out control circuit 1 is inputted with therefresh trigger signal RFTG in addition to the high-order refreshaddress Add(C) (m). A refresh permission signal RFEN used as an outputsignal thereof is inputted to the word driver 18 (control method (1)) orthe refresh controller section 15 (control method (2)).

[0091] In the semiconductor memory device according to the firstembodiment, it is required that the external access operation requiredby the input of the control signal from the control terminal 101, andthe refresh operation required for each predetermined time from thebuilt-in refresh timing timer section 14 are performed independently ofeach other. Thus, the access arbiter 16 makes an adjustment between therequest signals REQ(O) and REQ(I) to thereby determine the operation tobe executed. Described specifically, the control signal inputted fromthe control terminal 101 is inputted to the I/O controller section 13from which an external access request is outputted to the access arbiter16 as the external-access request signal REQ(O). The refresh triggersignal RFTG outputted from the refresh timing timer section 14 isdirectly outputted to the access arbiter 16 as the refresh requestsignal REQ(I) corresponding to a request for the refresh operation inthe case of the control method (1), and is outputted thereto as therefresh request signal REQ(I) corresponding to the request for therefresh operation via the refresh controller section 15 in the case ofthe control method (2).

[0092] When either one of the external-access request signal REQ(O) andthe refresh request signal REQ(I) is outputted to the access arbiter 16,the access arbiter 16 controls the row-system controller section 17 toexecute the operation required. When the operation requests compete witheach other, the access arbiter 16 makes arbitration to theexternal-access request signal REQ(O) and the refresh request signalREQ(I) to thereby control the row-system controller section 17, wherebythe external access operation and the refresh operation are sequentiallyperformed in a continuous form.

[0093] The row-system controller section 17 outputs a control signalCTL1 according to the result of arbitration by the access arbiter 16 andselects an address signal (Add(O) or Add(C)) to be inputted to the rowpre-decoder 102. Further, the row-system controller section 17 outputs acontrol signal CTL2 to allow the main row decoder 103 to further decoderpre-decode signal AD(1) predecoded by the row pre-decoder 102 andactivate the word driver 18 with suitable timing for thereby activatinga word line (any of WL0 through WLn) selected by its decoding. Namely,the row-system controller section 17 sequentially outputs a series ofthe control signals CTL1 and CTL2 having a suitable timing differencetherebetween, based on a start-up signal sent from the access arbiter16.

[0094] When, for example, the external-access request signal REQ(O) andthe refresh request signal REQ(I) are simultaneously inputted, theaccess arbiter 16 needs to determine the priority of an operationsequence. The access arbiter 16 is also capable of precedently selectingcontrol for giving priority to avoidance of the disappearance ordestroying of data and allowing the refresh operation to be placed aheador control for giving priority to a response to an external access andallowing the refresh operation to be placed ahead. Regardless of theorder of the operation sequence, a cycle time tCE is defined by bothcontinuous operations.

[0095] The refresh-thinning-out function will next be explained. Therefresh-thinning-out control circuit 1 judges for each refreshoperation, whether the refresh operation can be executed, and outputs arefresh permission signal RFEN. The first embodiment illustrates the twomethods of controlling the refresh-thinning-out operation according tothe refresh permission signal RFEN ((1) and (2) in FIG. 1).

[0096] The control method (1) will first be described. According to thecontrol method (1), when a refresh trigger signal RFTG is outputted fromthe refresh timing timer section 14, the refresh address counter 12 iscounted up to output new refresh address Add(C). Predeterminedhigh-order bits of the refresh address are inputted to therefresh-thinning-out control circuit 1 as a high-order refresh addressAdd(C) (m), where a decision as to whether a refresh operation for thenewly-set refresh address Add(C) can be executed, is made.

[0097] If, for example, the refresh address Add(C) other than the leastsignificant bit is inputted to the refresh-thinning-out control circuit1 although one inputted to the refresh-thinning-out control circuit 1 isdefined as the high-order refresh address Add(C) (m) of thepredetermined high-order bits, then the unit of criterion or judgment isset with two word lines as one unit. If the refresh address Add(C) otherthen two low-order bits is inputted thereto, then the unit of criterionor judgment is set with four word lines as one unit. The unit ofcriterion can be freely set according to the setting of high-order bits.Further, the refresh-thinning-out control circuit 1 may take aconfiguration wherein all the bits of the refresh address Add(C) areinputted thereto without except for the low-order bits to make decisionsevery word lines.

[0098] A refresh permission signal RFEN indicative of the result ofdetermination is inputted to the word driver 18 so that the activationof the word driver 18 is controlled. When the execution of the refreshoperation is permitted by the refresh permission signal RFEN, the worddriver 18 is activated. When the execution of the refresh operation isprohibited, the word driver 18 is maintained at a deactivated state.

[0099] On the other hand, a refresh trigger signal RFTG outputted fromthe refresh timing timer section 14 is inputted even to the accessarbiter 16 as a refresh request signal REQ(C). In parallel with theprocess of judgment by the refresh-thinning-out control circuit 1, anadjustment to an access operation is made between the refresh triggersignal RFTG and the external-access request signal REQ(O), and controlon the row system for decoding an address signal (Add(O) or Add(C)) tothereby select the corresponding word line is performed. Namely, whenthe refresh operation is controlled by the access arbiter 16, therow-system controller section 17 is started up to output a controlsignal CTL1. Thus, the row pre-decoder 102 pre-decodes the refreshaddress Add(C) and the main row decoder 103 decodes pre-decode signalAD(1) in response to a control signal CTL2 outputted after predeterminedcontrol timing, so that a word line intended for the refresh operationis selected.

[0100] The decision by the refresh-thinning-out control circuit 1 as towhether or not the refresh operation is executable, is made according towhether the high-order refresh address Add(C) (m) intended for therefresh operation corresponds to predetermined address stored inadvance, based on data-holding characteristics of each memory cell,which discriminate whether the refresh operation is executable. Namely,the above judgment is basically performed by a comparison between theaddresses. On the other hand, it is necessary to sequentially carry outmany processes, as processes up to the driving of each word line, suchas a first-come decision between the request signals REQ(O) and REQ(I)by the access arbiter 16, a decode process made via a multistage logicgate by the pre/main decoders 102 and 103, and a boosting process fordriving each word line by the word driver 18, etc.

[0101] Thus, a processing time interval from the refresh trigger signalRFTG to the selection of each word line by the main row decoder 103generally becomes longer than a decision time interval from the refreshtrigger signal RFTG to the refresh permission signal RFEN. Therefore,the process of judgment by the refresh-thinning-out control circuit 1 asto whether the refresh operation is executable, can be perfectlyembedded in a processing time interval of the row system.

[0102] Since the corresponding word line is selected by decoding of themain row decoder 103 after the setting of the word driver 18 to anactive state when the execution of the refresh operation is permitted bythe refresh-thinning-out control circuit 1, the refresh operation isperformed without increasing the processing time of the row system.Since the decoding of the main row decoder 103 is executed with beingdelayed with respect to the setting of the word driver 18 to an inactivestate where the execution of the refresh operation is prohibited, therefresh operation is not executed without driving the corresponding wordline selected by the decoding.

[0103] Incidentally, while the first embodiment has described the casein which the refresh permission signal RFEN is used to control theactivation of the word driver 18, the control on the activation thereofby the refresh permission signal RFEN may be effected on the pre-stagecircuits such as the main row decoder 103 as an alternative to the worddriver 18 if the processing time for the judgment of therefresh-thinning-out control circuit 1 is sufficient, from arelationship with the time required for the decode processing of therefresh address Add(C), which is performed between the row pre-decoder102 and the word driver 18.

[0104] The control method (2) will next be explained. Predeterminedhigh-order bits of new refresh address Add(C) produced by count-up ofthe refresh address counter 12 based on a refresh trigger signal RFTGare inputted to the refresh-thinning-out control circuit 1 as high-orderrefresh address Add(C) (m) in a manner similar to the control method(1), where a decision as to whether the refresh operation is executable,is made.

[0105] In the control method (2), there is provided the refreshcontroller section 15 for outputting a refresh trigger signal RFTG tothe access arbiter 16 as a refresh request signal REQ(I). A refreshpermission signal RFEN indicative of the result of determination isinputted to the refresh controller section 15, which is then activatedand controlled to thereby control the output of the refresh requestsignal REQ(I). When the execution of the refresh operation is permittedby the refresh permission signal RFEN, the refresh request signal REQ(I)is outputted to the access arbiter 16. When the execution of the refreshoperation is prohibited, no refresh request signal REQ(I) is outputted.

[0106] Namely, the refresh request signal REQ(I) is outputted to theaccess arbiter 16 according to the result of determination as to whetherthe refresh operation at the refresh address Add(C) set with respect tothe refresh trigger signal RFTG is executable. On the other hand, anexternal-access request signal REQ(O) is outputted from the I/Ocontroller section 13 whenever necessary according to a control signalinputted from the control terminal 101. Thus, when the external accessoperation and the refresh operation are in a state of competition, therefresh request signal REQ(I) is outputted with being delayed by a timeinterval required to discriminate whether the refresh operation isexecutable, with respect to the external-access request signal REQ(O).

[0107] Namely, there is a possibility that although the refreshoperation is essentially placed ahead and the external access operationis to be executed successively, the refresh request signal REQ(I) willbe inputted to the access arbiter 16 with being delayed with respect tothe external-access request signal REQ(O) due to the delay equivalent tothe judgment time interval where an external access request is issuedsubsequently to the refresh trigger signal RFTG or accesses aresimultaneously made according to the settings in a state of competitionof the accesses. Since the process of determination by therefresh-thinning-out control circuit 1 can be perfectly embedded into apreceding external access operation although an operation sequence isreversed, a cycle time defined by the continuous operations of theexternal access operation and the refresh operation becomes no long withrespect to the original provision.

[0108] When the refresh operation is prohibited underrefresh-thinning-out control, a series of processing operations of therow system from the process of an adjustment to each request signal tothe process of decoding each address, further, the process of drivingeach word line are prohibited upon the refresh operation. Unnecessarycurrent consumption can be reduced.

[0109] Incidentally, since the setting of the number of bits of thehigh-order refresh address Add(C) (m) having a predetermined high-orderbits is similar to the case of the control method (1), and similaroperation/effects are brought about, the description thereof herein willbe omitted.

[0110]FIG. 2 shows an example of the input of high-order refresh addressAdd(C) (m) to the refresh-thinning-out control circuit 1. A dedicatedaddress decoder 1A is provided at an input stage of therefresh-thinning-out control circuit 1. A dedicated decode signal AD(2)decoded according to the input high-order refresh address Add(C) (m) isinputted to a refresh-thinning-out controller section 19 for making adecision as to refresh thinning out.

[0111] Since the dedicated decode signal AD(2) is a decode signalobtained by decoding the high-order refresh address Add(C) (m), the unitof judgment as to the execution/non-execution of the refresh operationby the refresh-thinning-out controller section 19 can be expanded by thenumber of bits of an excepted low-order address according to thehigh-order refresh address Add(C) (m) inputted to the dedicated addressdecoder 1A. If the number of bits of the low-order address to beexcepted is suitably set, then the determination as to theexecution/non-execution of the refresh operation can be performed in asuitable decision unit. While an increase in die size due to a fuse orthe like for storing an address used for setting the presence or absenceof refresh thinning out for each predetermined word line is beingsuppressed, a decision as to whether refresh thinning out is executable,is made for each predetermined unit of word lines to thereby make itpossible to reduce current consumption.

[0112]FIG. 3 shows a layout example suitable for being equipped with adedicated address decoder 1A. FIG. 3 corresponds to a case in whichrefresh address counter 12 is depressively disposed in the neighborhoodof row address buffers 11 disposed every address terminals 101. Therefresh address counters 12 and the refresh-thinning-out controllersection 19 are disposed away from one another.

[0113] In such a layout, an address signal inputted to therefresh-thinning-out controller section 19 is also considered to be setas pre-decode signal AD(1) outputted from the row pre-decoder 102.However, since a wiring path up to the refresh-thinning-out controllersection 19 is long, a capacitance load CLD attendant on the pre-decodesignal AD(1) increases due to parasitic capacitance of a wiring, and thelike. Since the pre-decode signal AD(1) is inputted even to the main rowdecoder 103 to carry out the selection of each word line, a processingtime interval of the row system up to the selection of each word linemight be delayed as a result of a drive delay of the pre-decode signalAD(1) due to the substantial capacitance load CLD.

[0114] Thus, the dedicated address decoder 1A is provided to allow thededicated decode signal AD(2) to have charge of the propagation of theaddress signal to the refresh-thinning-out controller section 19. Theunnecessary capacitance load CLD is eliminated from the pre-decodesignal AD(1) inputted to the main row decoder 103, so that the drivedelay of the pre-decode signal AD(1) can be brought to the requiredminimum.

[0115] A second embodiment shown in FIG. 4 corresponds to a case inwhich in a manner similar to the first embodiment, arefresh-thinning-out function is added to operation specs in which abuilt-in refresh operation and an external access operation areactivated independently of each other with occasional timings. Thepresent embodiment is a semiconductor memory device wherein arefresh-thinning-out function is provided after compatibility of apseudo SRAM or the like to an SRAM or the like has been made morecomplete, whereby even a reduction in current consumption at standby canbe achieved.

[0116] The second embodiment is provided with a refresh-thinning-outcontrol circuit 2 inputted with pre-decode signal AD(1) outputted from arow pre-decoder 102, as an alternative to the refresh-thinning-outcontrol circuit 1 inputted with the refresh address Add(C).

[0117] A judgment process by comparison between addresses is generallyperformed in a short period of time with respect to sequential processesup to the driving of each word line, such as a decode process made via amultistage logic gates by a main decoder 103, and a boosting process fordriving each word line by a word driver 18, etc. Thus, the process ofmaking a decision as to the execution/non-execution of the refreshoperation by the refresh-thinning-out control circuit 2 can be perfectlyembedded in a processing time interval of a row system in a mannersimilar to the case of the control method (1) according to the firstembodiment.

[0118] Since the present embodiment takes such a configuration as tosupply the pre-decode signal AD(1) outputted from the row pre-decoder102, a dedicated address decoder becomes unnecessary and an increase indie size in the semiconductor memory device can be suppressed. Since thepresent embodiment is similar in other configuration to the controlmethod (1) of the first embodiment and brings about similar operationsand effects, the description thereof herein will be omitted.

[0119]FIG. 5 shows an example of the input of the pre-decode signalAD(1) to the refresh-thinning-out control circuit 2. A buffer section 2Ais provided at an input stage of the refresh-thinning-out controlcircuit 2, which is capable of taking in or capturing the inputpre-decode signal AD(1) according to a control signal SELC. The buffersection 2A can be made up of an AND logic gate, for example.Alternatively if such a configuration that the input of the pre-decodesignal AD(1) can be controlled based on the control signal SELC, istaken therefor, it is then needless to say that it can be applied to thebuffer section. The buffer section may be made up of a transfer gate orthe like controlled by the control signal SELC.

[0120]FIG. 6 shows a layout example suitable for being equipped with abuffer section 2A as an alternative to the dedicated address decoder 1Ashown in FIG. 3. In this case, the buffer section 2A is disposed in thevicinity of a row pre-decoder 102. Incidentally, the present example issimilar to the case of FIG. 3 in that refresh address counters 12 aredepressively disposed in the neighborhood of row address buffers 11disposed every address terminals 101, and the refresh address counter 12and a refresh-thinning-out controller section 19 are disposed away fromone another.

[0121] In such a layout, a substantial capacitance load CLD parasitic ona long wiring path or route from the row pre-decoder 102 to therefresh-thinning-out controller section 19 is segmented or divided bythe buffer section 2A disposed in the neighborhood of the rowpre-decoder 102. Therefore, a drive delay of the pre-decode signal AD(1)can be brought to the required minimum without adding the unnecessarycapacitance load CLD to the path for the pre-decode signal AD(1) fromthe row pre-decoder 102 to the main row decoder 103.

[0122] Access operation waveforms employed in the first and secondembodiments will next be illustrated in FIGS. 7 through 11. FIG. 7corresponds to a case in which a refresh request and an external accessrequest compete with each other in a pseudo SRAM. FIG. 7 illustrates acase in which the refresh request precedes the external access request(see operation waveforms on the left side in FIG. 7) and a case in whichboth access requests are simultaneously produced (see operationwaveforms on the right side in FIG. 7). When the access requests aretaken simultaneously, the setting of giving precedence to the refreshoperation will now be shown.

[0123] A decision or judgment as to execution/non-execution of therefresh operation is normally performed during the refresh operation.Described specifically, refresh address Add(C) produced based on arefresh command signal φCBR outputted from a CBR judgment circuit 133 isdiscriminated by a refresh-thinning-out control circuit 105 in FIG. 24,and the result of judgment is outputted from the refresh-thinning-outcontrol circuit 105 as a refresh permission signal φ2, so that an ANDlogic gate 400 b is gated to output an activation signal φR. Theactivation signal φR is a signal for activating a row address decoder137 and is also a signal corresponding to the control signal CTL1 firstoutputted from the row-system controller section 17 employed in each ofthe first and second embodiments. Namely, in FIGS. 24 and 25, thedecoding of a row address is started after the process of judgment bythe refresh-thinning-out control circuit 105, and a judgment ordiscrimination time is added to the time required to execute the refreshoperation.

[0124] The operation waveform in the normal or ordinary case in FIG. 7shows that this judgment time tJ is added aside from an execution timeat the refresh operation. Therefore, a judgment time tJ for judgingwhether refresh thinning out is executable, is added in addition to thetime required to execute the refresh operation and the external accessoperation, whereby a cycle time tCE′ at the time that accesses competewith each other, is defined. Since the continuous execution time for therefresh operation and the external access operation corresponds to acycle time tCE at the access competition where no thinning-out controlis done, the judgment time tJ is added to this time to thereby define acycle time tCE′ (=tCE+tJ), thus incurring an increase in cycle time.

[0125] On the other hand, the judgment time tJ is embedded or charged inthe time required to execute the refresh operation or the time requiredto execute the external access operation in the first and secondembodiments. In the case of the control method (1) of the firstembodiment, and the second embodiment, the refresh trigger signal RFTGis inputted to the access arbiter 16 as the refresh request signal.Based on the refresh address Add(C) outputted from the refresh triggersignal RFTG, thinning-out is judged or discriminated and the refreshoperation is started. Since the judgment time tJ is embedded in a firsthalf of the execution time of the refresh operation, a judgment processdoes not rat-control the original refresh operation, and the cycle timetCE is defined by the continuous execution time for the refreshoperation and the external access time.

[0126] In the case of the control method (2) of the first embodiment,thinning-out judgment is performed precedently based on the refreshaddress Add(C) outputted from the refresh trigger RFTG. Since therefresh controller section 15 is maintained at its inactive state duringthis period, no refresh request signal REQ(I) is outputted to the accessarbiter 16. If the external-access request signal REQ(O) is generatedduring a period for this judgment process, then the external accessoperation is performed precedentially. Since the judgment process isembedded in a first half of the time required to execute the externalaccess operation, the judgment process neither rate-controls theoriginal refresh operation nor the external access operation. Therefore,a cycle time tCE is defined by the time required to continuously executethe refresh operation and the external access operation. Incidentally, acompetition operation in this case is started from the point of time ofoccurrence of the external-access request signal REQ(O) with beingdelayed from the time of occurrence of the precedent refresh triggersignal, whereas the external access operation is not delayed from theoriginal access.

[0127]FIGS. 8 through 11 respectively show a case in which refreshoperations are embedded in burst operations in a synchronoussemiconductor memory device such as a pseudo SSRAM or the like. FIGS. 8and 9 illustrate a burst length 1, and FIGS. 10 and 11 show amulti-burst length.

[0128] Here, the embedding of the refresh operation indicates operationspecs in which a refresh operation is embedded in a burst cycle so thateven the refresh operation can be executed without interruption of theburst operation.

[0129] The operation of the burst length 1 in the normal case shown inFIG. 8 corresponds to the execution of a read operation (operation atRDA command) with an auto precharge operation with CAS latencies 3. Asdescribed in FIG. 7, there is a case in which a decision as to theexecution/non-execution of the refresh operation must be performed inthe refresh-thinning-out function. Namely, it shows a case in which arefresh request signal REQ(I) is produced at a clock CLK9 in which aburst operation is finished and an equalize operation of each bit lineis being performed. If the refresh-thinning-out function is absent, thenthe equalize operation is completed in a cycle of the clock CLK9 (highlevel period of signal EQ in FIG. 8). Thereafter, when a word line WLfor the refresh operation rises in a cycle of a clock CLK10, a refreshrequest signal REQ(I) is generated at the clock CLK9 by therefresh-thinning-out function. Therefore, when the refresh operation ispermitted after the determination as to the execution/non-execution ofthe refresh operation has been made, the process of decoding refreshaddress (C) is performed in a cycle of a clock CLK10 in the next cycle.Namely, with the introduction of the refresh-thinning-out function, ajudgment time equivalent to one cycle is required and a dedicated clockcycle must be added by one cycle (clock CLK10 in FIG. 8). As comparedwith a case in which a RAS cycle time tRAS in the absence of therefresh-thinning-out function is 15 clock cycles, 16 clock cycles addedwith one clock cycle are needed.

[0130] On the other hand, the operation waveforms of FIG. 9 show ones inthe case of the control method (1) employed in the first embodiment, andthe second embodiment. As described in FIG. 7, a judgment process isembedded in an address decode time for the refresh operation. Since thejudgment process and the process of decoding refresh address Add(C) areparallel-processed in the same clock cycle (clock CLK9 in FIG. 9), theaddition of a dedicated clock cycle is not necessary even if therefresh-thinning-out function is introduced. A RAS cycle time is 15clock cycles identical to the RAS cycle time tRAS in the case of theabsence of the refresh-thinning-out function, and the refresh operationhaving the refresh-thinning-out function can be embedded.

[0131]FIG. 10 shows operation waveforms of burst lengths 16 as anoperation of a multi-burst length in a normal or ordinary case. This isequivalent to a case in which a read operation (operation at RDAcommand) with an auto precharge operation is performed with CASlatencies 3. Upon the operation of the multi-burst length, for embeddinga refresh operation shown in FIG. 10, the opening/closing of a switch atreading of data from each bit line pair (BL and /BL) is not synchronizedwith a clock CLK and operated in a cycle faster than it. Namely, thedata is read prior to read timing based on the clock CLK. Theprecedentially-read data is stored in a temporary holding circuit (notshown) such as a data buffer circuit or the like and takes such specs asto be outputted outside in synchronism with a clock CLK corresponding toits subsequent read timing. Since the data is read precedentially, eachbit line pair (BL and /BL) can be equalized with timing faster than inthe case of external specs. Therefore, the operation can be transitionedto an equalize operation at a clock CLK13.

[0132] As to the refresh-thinning-out function, however, there is a casein which a decision as to the execution/non-execution of a refreshoperation must be made independently in a manner similar to theoperation of the burst length 1 (see FIG. 8) even in this case. Namely,when a refresh request signal REQ(I) is produced at a clock CLK13 atwhich the equalize operation of each bit line is being performed, theprocess of decoding refresh address Add(C) must be performed at a clockCLK14 at which a word line WL for the refresh operation rises, in theabsence of the refresh-thinning-out function. Namely, with theintroduction of the refresh-thinning-out function, a dedicated clockcycle must be added by one cycle (clock CLK14 in FIG. 10). As comparedwith a case in which a RAS cycle time tRAS in the absence of therefresh-thinning-out function is 20 clock cycles, 21 clock cycles addedwith one clock cycle are needed.

[0133] On the other hand, the operation waveforms of FIG. 11 show onesin the case of the control method (1) employed in the first embodiment,and the second embodiment. In a manner similar to FIG. 9, a judgmentprocess is embedded in an address decode time for the refresh operation.Since the judgment process and the process of decoding refresh addressAdd(C) are parallel-processed in the same clock cycle (clock CLK13 inFIG. 11), the addition of a dedicated clock cycle is not necessary evenif the refresh-thinning-out function is introduced. A RAS cycle time is20 clock cycles identical to the RAS cycle time tRAS in the absence ofthe refresh-thinning-out function, and the refresh operation having therefresh-thinning-out function can be embedded.

[0134] Incidentally, while the operations have been described in FIGS. 9and 11 assuming the control method (1) of the first embodiment and thesecond embodiment, the judgment process can be embedded even in thecontrol method (2) of the first embodiment. Since this is similar to thedescription of the access competition in the pseudo SRAM in FIG. 7, thedescription thereof herein will be omitted.

[0135] According to the control method (1) of the first embodiment andthe second embodiment as described in detail above, the judgment processas to the execution/non-execution of the refresh operation in each ofthe refresh-thinning-out control circuits 1 and 2 can be embedded in thetime required to perform decode processing of the refresh address Add(C)indicative of the corresponding address. Therefore, the judgment time tJrequired for the execution/non-execution of the refresh operation isadded to the cycle time tCE corresponding to the execution time at theaccess for competition 10 with the external access operation includingthe refresh operation, and hence the cycle time tCE does not increase.Even in the case of the operation specs in which the refresh operationis embedded in the burst operation, the judgment time tJ is not added tothe RAS cycle time tRAS and hence the RAS cycle time tRAS does notincrease without increasing the clock cycle.

[0136] According to the control method (2) of the first embodiment aswell, since the refresh request signal REQ(I) is not used as theadjustment signal without being inputted to the access arbiter 16 at thestage prior to the judgment as to the execution/non-execution of therefresh operation in the refresh-thinning-out control circuit 1, theexternal access operation is immediately preformed if theexternal-access request signal REQ(O) is produced during the process forthe judgment as to the execution/non-execution thereof. The time tJrequired to make a judgment as to the execution/non-execution thereof isnot added as the delay of the external access operation. Accordingly,the judgment time tJ is not added to the cycle time tCE corresponding tothe execution time at the access for competition with the externalaccess operation including the refresh operation, and hence the cycletime tCE does not increase. Even in the case of the operation specs inwhich the refresh operation is embedded in the burst operation, thejudgment time tJ is not added to the RAS cycle time tRAS and hence theRAS cycle time tRAS does not increase without increasing the clockcycle.

[0137] When the judgment for prohibiting the refresh operation is madeto the refresh request signal REQ(I), the refresh request signal REQ(I)is not made available for adjustments between the refresh request signalREQ(I) and the external-access request signal REQ(O). Namely, when therefresh operation is judged to be prohibited, the process of decodingthe refresh address Add(C) indicative of the corresponding address,subsequent to the access arbiter 16 corresponding to a requestsignal-to-request signal adjustor section is not operated, andunnecessary circuit operations are eliminated, thereby making itpossible to reduce current consumption.

[0138] According to the dedicated address decoder 1A employed in thefirst embodiment, the refresh-thinning-out controller section 19 may beequipped with a storage section comprised of a fuse, a ROM, a RAM or thelike for each decoded dedicated decode signal AD(2) corresponding to acorresponding address group. As compared with the case in which it isprovided for each address for the corresponding word line intended forthe refresh operation, the exclusively possessed area of the storagesection to a die size of a semiconductor memory device can be reduced.

[0139] The designation of the dedicated decode signal AD(2) necessaryfor the judgment as to the execution/non-execution of the refreshoperation is performed by providing the dedicated address decoder 1Aused as the dedicated decoder to thereby decode the high-order refreshaddress Add(C) (m) indicative of the corresponding address intended forthe refresh operation. Therefore, the load on the row pre-decoder 102will not increase upon the judgment as to the execution/non-execution ofthe refresh operation. Even when the determination as to theexecution/non-execution of the refresh operation is an unnecessarysetting or even in the case of the external access operation, the loadimposed on the row pre-decoder 102 will not increase. Even when thefunction of judging whether the refresh operation is executable, isintroduced, an increase in the load on the access operation is notincurred, and an increase in current consumption, a delay in cycle time,etc. are not brought about.

[0140] Since the dedicated decode signal AD(2) can be specifiedindependently by the dedicated address decoder 1A, the number ofoccurrencies of the refresh request signal REQ(I) collected up as a unitfor judgment is set without any restriction on the decode processing ofthe row pre-decoder 102 to thereby make it possible to specify ordesignate the dedicated decode signal AD(2). Since the units ofdecisions made as to whether the refresh operation is executable, arecollected up every dedicated decode signal AD(2), the decision as toexecution of the refresh operation might be made inclusive of each wordline requiring no execution of the refresh operation. However, thenumber of occurrencies of the refresh request signal REQ(I) collected upfor each dedicated decode signal AD(2) is adjusted by the selection ofthe high-order refresh address Add(C) (m) to thereby make it possible torealize a reduction in current consumption by refresh-thinning-out whilean increase in the exclusively possessed area of the storage section isbeing suppressed.

[0141] According to the second embodiment, the row pre-decoder 102 canshare the designation of the pre-decode signal AD(1) indicative of thecorresponding address group for making a decision as toexecution/non-execution of the refresh operation. Even if the functionof judging whether the refresh operation is executable, is introduced,an increase in die size of the semiconductor memory device can besuppressed.

[0142] As a third embodiment, a circuit block diagram of arefresh-thinning-out control circuit is shown in FIG. 12. A refreshtrigger signal RFTG is inputted to its corresponding switching section31 in a refresh-thinning-out controller section 19. The switchingsection 31 outputs a switching control signal SELC for performingswitching between activity and inactivity of refresh-thinning-outcontrol according to the refresh trigger signal RFTG. The switchingcontrol signal SELC is inputted to a comparator section 33 and ajudgment section 34 and serves so as to control the activation of thesecircuits. The switching control signal SELC is inputted even to adedicated address decoder 1A or a buffer section 2A, where theactivation is controlled similarly.

[0143] The comparator section 33 is inputted with pre-decode signalAD(1) or dedicated decode signal AD(2) intended for judgment as to theexecution/non-execution of a refresh operation from the dedicatedaddress decoder 1A or the buffer section 2A and performs addresscomparison between the signal and predetermined address AD(TO) includingor corresponding to each word line connected to its corresponding memorycell having predetermined data-holding characteristics stored in astorage section 32. Here, it is needless to say that the predeterminedaddress AD(TO) is decode signal having the same level as the pre-decodesignal AD(1) or the dedicated decode signal AD(2). The storage section32 and the comparator section 33 constitute a refresh-ability recordersection 30.

[0144] The result of comparison by the comparator section 33 isoutputted to the judgment section 34 from which a refresh permissionsignal RFEN is outputted according to the state of setting of theswitching control signal SELC.

[0145] In the refresh-thinning-out refresh control illustrated as thethird embodiment as described above, the dedicated address decoder 1A orbuffer section 2A, the comparator section 33 and the judgment section 34are deactivated by the switching control signal SELC outputted from theswitching section 31 where a refresh-thinning-out operation is notexecuted. It is therefore possible to reduce current consumption madedue to unnecessary circuit operations.

[0146]FIG. 13 shows a specific example of the switching section 31employed in the third embodiment. A refresh timing timer section 14comprises an oscillator circuit and a divider. The refresh timing timersection 14 divides an oscillation signal produced from the oscillatorcircuit to output each refresh trigger signal RFTG. The switchingsection 31 has a counter made up of a predetermined number offlip-flops. The switching section 31 counts the number of occurrences ofthe refresh trigger signal RFTG to thereby measure or time a refreshcycle tREF.

[0147] Since word lines are sequentially selected every refresh triggersignals RFTG and refresh requests are made, a refresh cycle tREF can betimed if the outputs of the refresh trigger signals RFTG correspondingto the number of word lines to be refreshed, are counted. If the settingof execution of refresh-thinning-out control every 2 cycles of therefresh cycle tREF is taken, then the switching control signal SELC isswitched for each timing of the refresh cycle tREF to thereby make itpossible to perform switching between activity and inactivity of therefresh-thinning-out control.

[0148] Since the refresh cycle tREF can be timed by counting the numberof the outputs of the refresh trigger signals RFTG, the processes suchas the initialization of the refresh address Add(C) or the storage ofthe initial value, etc., which have been required for the method ofmaking a circuit of the refresh address Add(C) to thereby time ormeasure the refresh cycle tREF, become unnecessary. The circuits forperforming the processes such as the initialization or the storage ofthe initial value become unnecessary, and the simplification of thecontrol circuit and a reduction in current consumption can be achieved.

[0149]FIG. 14 shows a specific example of the dedicated address decoder1A employed in the third embodiment. In the specific example of FIG. 14,high-order 4 bits of refresh address Add(C) are selected as units forjudgment as to the execution/non-execution of a refresh operation, whichbits are defined as high-order refresh addresses Add(C)(N-3) through(N). Here, N indicates the most significant bit. The high-order refreshaddresses Add(C)(N-3) through (N) are inputted to their correspondingNAND logic gates together with a switching control signal SELC.Positive/negative complementary signals are produced from the outputs ofthe respective NAND logic gates and the outputs of ANDing of all thecombinations every addresses are produced to thereby execute decoding.Decode signals AD0 through AD3 are respectively signals relative tocombinations of (0, 0), (0, 1), (1, 0) and (1, 1) with respect to therefresh addresses Add(C) (N-3) and (N-2), whereas decode signals BD0through BD3 are respectively signals for combinations of (0, 0), (0, 1),(1, 0) an (1, 1) with respect to the refresh addresses Add(C) (N-1) and(N). Incidentally, decode processing is activated when the switchingcontrol signal SELC is of a high logical level, whereas it is fixed to apredetermined output regardless of address values when it is of a lowlogical level, thus resulting in non-activation.

[0150]FIG. 15 is a specific example of the refresh-ability recordersection 30 employed in the third embodiment. An output terminal n1 of aNAND logic gate to which a switching control signal SELC and a refreshtrigger signal RFTG are inputted, is connected to an input terminal ofseries-connected inverter logic gates of two stages. Further, the outputterminal n1 is connected to an input terminal of another NAND logic gatetogether with an output terminal n3 of the inverter logic gatecorresponding to the second stage, and an output terminal n4 of the NANDlogic gate is connected to its corresponding gate terminal of a PMOStransistor. One terminal of the PMOS transistor is connected to apower-supply voltage. The decode signals AD0 through AD3 and BD0 throughBD3 decoded by the dedicated address decoder 1A are inputted to theircorresponding NAND logic gates together with the output terminal n2 ofthe first-stage inverter gate and thereafter inverted by theircorresponding inverter logic gates, whereby pulse decode signals A0through A3 and B0 through B3 are outputted.

[0151] The pulse decode signals A0 through A3 and B0 through B3 arerespectively combined together and inputted to their corresponding gateterminals of series-connected NMOS transistors of respective two stagesin 16 combinations. One terminals of rows of the 16 pairs of NMOStransistors each having a two-stage configuration are connected to theircorresponding ground voltages, whereas the other terminals thereof areconnected to a drain terminal of the PMOS transistor at a terminal n5through fuse elements F0 through F15. The terminal n5 is connected toits corresponding input terminal of an inverter logic gate, and arefresh judgment signal RFJG is outputted from an output terminal of theinverter logic gate.

[0152] In FIG. 15, the fuses (F0 through F15) are cut out with respectto the pulse decode signals inclusive of word lines connected withmemory cells good in data-holding characteristics and capable ofthinning-out refresh operations. A word line designated by the pulsedecode signals (A0, B0) corresponding to a non-cutout fuse (fuse 0 (F0)in FIG. 15) includes memory cells each of which is poor in data-holdingcharacteristics and must execute a refresh operation for each refreshcycle tREF.

[0153]FIG. 16 is a specific example of a first judgment sectionconstituting the judgment section 34 employed in the third embodiment.The first judgment section is provided with respective NAND logic gateseach inputted with a refresh judgment signal RFJG or a refresh triggersignal RFTG. A switching control signal SELC and its inverted signal arerespectively inputted to other input terminals. Output terminals of thepair of NAND logic gates are connected to their corresponding inputterminals of a NAND logic gate, and a refresh permission signal RFEN isoutputted from its output terminal.

[0154]FIG. 17 shows operations waveforms for describing operations ofthe refresh-ability recorder section (FIG. 15) and the first judgmentsection (FIG. 16). In FIG. 17, (A) shows the selection of the pulsedecode signals (A0, B0), and (B) indicates the selection of the pulsedecode signals (A1, B0) through (A3, B3).

[0155] Operations common to the respective (A) and (B) will first beexplained. When a pulse signal of a high logical level is inputted tothe refresh trigger signal RFTG and a refresh request is issued in astate in which the switching control signal SELC is brought to a highlogical level and refresh-thinning-out control is being activated, alogically-inverted pulse signal having a low logical level is outputtedto the terminal n1 and further inverted and delayed, followed by outputof a pulse signal of a high logical level at the terminal n2. Similarly,a delayed pulse signal having a low logical level is outputted to theterminal n3. Based on the pulse signals of the low logical levels at theterminals n1 and n3, a pulse signal of a high logical level, which hasbeen expanded from the pulse at the terminal n1 to the pulse at theterminal n3, is outputted to the terminal n4. During this period, thePMOS transistor is turned off to stop the charging of the terminal n5 tothe power-supply voltage.

[0156] In the case of (A), the pulse decode signals A0 and B0 produce apulse signal having a high logical level, based on the pulse signal atthe terminal n2. Thus, the NMOS transistor row to which the pulse decodesignals A0 and B0 are inputted, is brought into conduction. Further,since the fuse 0 (F0) connected between the same row and the terminal n5is not cut off, the terminal n5 is discharged to the ground voltage soas to reach a low logical level. Since the terminal n4 is thereaftertransitioned to a low logical level, the PMOS transistor is brought intoconduction again to charge the terminal n5 to a high logical level. As aresult, a pulse signal of a low logical level is outputted at theterminal n5 and then inverted by the corresponding inverter logic gate,so that a pulse signal of a high logical level is outputted therefrom asa refresh permission signal RFEN.

[0157] In the case of (B), any combination of the pulse decode signals(A1, B0) through (A3, B3) outputs or produces a pulse signal of a highlogical level, based on a pulse signal at the terminal n2. Thus, thecorresponding NMOS transistor row inputted with any combination of thepulse decode signals (A1, B0) through (A3, B3) is brought intoconduction. However, since all the fuses (F1 through F15) connectedbetween the terminal n5 and each NMOS transistor row are cut off in thecase of (B), a path extending from the terminal n5 to the ground voltageis not established and the voltage at the terminal n5 is maintained atthe power-supply voltage. As a result, the voltage is inverted by theinverter logic gate and the resultant refresh permission signal RFEN ismaintained at a low logical level.

[0158] While the specific examples shown in FIGS. 14 and 15 haverespectively show the case in which the refresh address Add(C) (m) isset by the high-order 4 bits as seen from the most significant bit, thenumber of the high-order bits is not limited to it. Layout exclusivelypossessed areas of the fuses to be provided for the refresh-abilityrecorder section 30 and the effect of reducing current consumption bythe refresh-thinning-out function owing to the collection-up of therefresh-thinning-out control every plural word lines have a tradeoffrelationship. A suitable setting can be achieved while adjustments toboth are being made.

[0159]FIG. 18 is a specific example of the second judgment sectionconstituting the judgment section 34 employed in the third embodiment.The first judgment section (FIG. 16) performs a fuse cut-out processwhere word lines good in data-holding characteristics and capable ofthinning out a refresh operation are included, whereas in the secondjudgment section, the setting of performing a process for cutting offeach fuse where word lines relatively poor in data-holdingcharacteristics and incapable of thinning out a refresh operation areincluded, is performed.

[0160] Here, a refresh cycle tREF is determined according to the abilityof data-holding characteristics of each memory cell. Namely, there is aneed to effect refresh on each memory cell relatively poor indata-holding characteristics in a shorter period of time. Since therefresh cycle tREF is set under rate-control to each memory cell poor indata-holding characteristics, a decision as to theexecution/non-execution of a refresh operation is made to each memorycell relatively good in data-holding characteristics according to arefresh request signal, and the refresh operation may be effectedthereon as needed. However, there is a need to effect the refreshoperation on each memory cell relatively poor in data-holdingcharacteristics for each refresh request signal.

[0161] The second judgment section includes a 3-input NAND logic gate asan alternative to the NAND logic gate inputted with the switchingcontrol signal SELC and the refresh judgment signal RFJG in the judgmentsection (FIG. 16). A switching control signal SELC, a delay signalobtained by delaying a refresh trigger signal RFTG outputted to aterminal n11 by a predetermined delay time τ, and a pulse signal of alow logical level, which is obtained by expanding a pulse signal of ahigh logical level of a refresh judgment signal RFJG outputted to aterminal n12 by a predetermined time interval, are inputted to the3-input NAND logic gate.

[0162]FIG. 19 shows operation waveforms. In FIG. 19, (A) illustrates theselection of pulse decode signals (A0, B0), and (B) shows the selectionof pulse decode signals (A1, B0) through (A3, B3).

[0163] When a pulse signal of a high logical level is inputted to therefresh trigger signal RFTG in a state in which the switching controlsignal SELC is of a high logical level as an operation common to (A) and(B), a delayed pulse signal having a high logical level is outputted tothe terminal nil after the predetermined delay time τ.

[0164] Since the fuse 0 (F0) is not cut out in the refresh-abilityrecorder section 30 (FIG. 15) in the case of (A), a pulse signal of ahigh logical level is outputted therefrom as the refresh judgment signalRFJG. In the second judgment section, this pulse signal is logicallyinverted and then expanded in pulse width, which in turn is outputted tothe terminal n12 as a pulse signal of a low logical level. At this time,a predetermined delay time τ is set in such a manner that the pulsesignal having the high logical level outputted to the terminal n11 isembedded in a period of the pulse signal at the terminal n12. Thus, anyof the input terminals of the 3-inut NAND logic gate is inputted withthe signal of the low logical level, so that the output terminal n13 ismaintained at the high logical level. Since the output of other NANDlogic gate is also maintained at a high logical level here, a refreshpermission signal RFEN is maintained at a low logical level.

[0165] In the case of (B), the fuses (F1 through F15) are cut out in therefresh-ability recorder section 30 (FIG. 15) and a refresh judgmentsignal RFJG is maintained at a low logical level. Thus, the terminal n12is maintained at a high logical level in the second judgment section.Thus, a pulse signal of a low logical level is outputted to the outputterminal n13 of the 3-input NAND logic gate, based on a pulse signal ofa high logical level at the terminal n11, and hence a refresh permissionsignal RFEN is outputted as a pulse signal of a high logical level.

[0166] According to the specific example of the third embodiment asdescribed above, when the second judgment section is made effective, thelogic of cutting-off of each fuse and the meaning of the refreshjudgment signal RFJG are set in reversed form with respect to the casein which the first judgment section is made effective. Accordingly, thesetting for using the first and second judgment sections by switching iseffective. At the initial stage, the first judgment section is madeeffective and set to the logic of cutting off each fuse where eachmemory cell good in data-holding characteristics is included. When thememory cells good in data-holding characteristics increases due tofactors in manufacturing, and the fuse group provided for therefresh-ability recorder section 30 cannot cope with it, the firstjudgment section is switched to the second judgment section. Thus, sinceeach memory cell poor in data-holding characteristics is reversed to thelogic of performing the fuse cutout, the number of fuse cutouts can bereduced. The number of the fuses provided for the refresh-abilityrecorder section 30 can be limited and the exclusively possessed area ofthe fuse group can be suppressed.

[0167] The provision of one switching fuse can cope with the switchingbetween the first judgment section and the second judgment section. Forexample, the refresh permission signals RFEN outputted from therespective judgment sections are set so as to be supplied via theircorresponding transfer gates. Since only either one of the transfergates is brought into conduction, the control signals sent to therespective transfer gates have a complementary relationship. Reversingthe logic relation by the switching fuse allows the switching betweenthe judgment sections.

[0168] Predetermined addresses to be stored in the storage section 32 inthe refresh-ability recorder section 30 are selected or switchedaccording to the distribution of the data-holding characteristicsincluded in each memory cell in the semiconductor memory device tothereby allow switching to judgment as to the execution/non-execution ofa refresh operation. Therefore, the predetermined addresses to be storedin the storage section 32 can be switched to get fewer according to thedistribution of the data-holding characteristics. The layout number offuses or the like to be provided for the storage section 32 iscompressed to make it possible to suppress an increase in the die sizeof the semiconductor memory device.

[0169] Since the number of the predetermined addresses to be stored iscompressed, the procedure of executing storage processing of thepredetermined addresses into the storage section 32 can be lightened. Itis possible to shorten a processing time interval and reduce processingcost with it.

[0170] Incidentally, while a description has been made of the case inwhich the first judgment section is made effective at the initial stageupon the setting of the first/second judgment sections, the secondjudgment section may be made effective. It is further needless to saythat while a description has been made of the case in which theswitching between the first/second judgment sections is performed by thecorresponding fuse, memory means for storing the state of a RAM, a ROM,a register or the like other than the fuses may be used.

[0171] The first/second judgment sections may be switched according tocharacteristics varied according to use environments such as a usetemperature, a power-supply voltage to be used, etc. in addition toswitching made according to characteristic distributions measured upontests such as a delivery inspection, etc. where they are switchedaccording to the distribution of data-holding characteristics. If, inthis case, situation-vs-setting memory means is set to a rewritable RAMor the like as an alternative to the fuses, then the setting ofswitching between the judgment sections can be changed according tovariations in environment.

[0172]FIG. 20 shows a refresh-thinning-out control circuit 4 providedwith a test facilitating function. In order to input a pre-decode signalAD(1) or a dedicated decode signal AD(2), or a testing address signalsent from an external terminal 44 for test address input, a switchsection 41 switched by a test signal TEST is provided at an inputportion of a refresh-thinning-out controller section 19. An AND logicgate 42 and a test-result output section 43 both used for outputting arefresh permission signal RFEN to an external terminal 45 for the outputof a test result according to the test signal TEST are provided at anoutput portion of the refresh-thinning-out controller section 19.

[0173] In a normal or ordinary operating state, the test signal TEST isset to a low logical level, for example. The switch section 41 isconnected to the pre-decode signal AD(1) or the dedicated decode signalAD(2), so that the corresponding address signal to make a decision as tothe execution/non-execution of a refresh operation is inputted. Sincethe output of the AND logic gate 42 is fixed to a low logical level, thetest result output section 43 can be maintained at an inactive state.Accordingly, the external terminal 44 for the test address input and theexternal terminal 45 for the test result output can be used as terminalsother than for testing in this case.

[0174] In a test state, the test signal TEST is brought to a highlogical level, for example. The switch section 41 is connected to theexternal terminal 44 for the test address input so that anexternally-set address signal is inputted. Since a signal kept in phasewith a refresh permission signal RFEN is outputted to the output of theAND logic gate 42, a test result can be outputted to the externalterminal 45 for the test result output via the test result outputsection 43. In this case, the testing address can be freely inputtedfrom the external terminal 44, and necessary addresses can be suppliedpromptly and accurately for testing without waiting for control of abuilt-in refresh address counter or the like. It is possible to providethe test facilitating function effective for application to a failanalysis and a characteristic analysis.

[0175] According to the fourth embodiment as described above, the resultof judgment as to the execution/non-execution of the refresh operationby the refresh-thinning-out controller section 19 can be observedexternally as needed. Therefore, it can be made available for the failanalysis, characteristic analysis and the like of the semiconductormemory device, and a characteristic test can be executed efficiently.

[0176] Refresh-thinning-out control in a redundant region will bedescribed in FIGS. 21 through 23 as a fifth embodiment.

[0177]FIG. 21 is a first specific example. The present drawing is aflowchart for describing a process for cutting off even each fuse forindicating a redundant region through the use of redundant setting dataupon cutting off of each fuse for storing each address forrefresh-thinning-out control.

[0178] A data collecting process stage will first be described. In Step(hereinafter abbreviated as “S”) 10, redundant data is acquired. Addressdata related to each of fail or defective memory cells defective inoperating characteristics is acquired. These memory cells in an addressregion are intended for the use of a redundant region. The acquired datais stored as redundant address data (D1). Further, data-holdingcharacteristics stored in the corresponding memory cell are acquired(S20). Data for determining a region for performing thinning-out controlon a refresh operation is acquired according to good/bad states of thedata-holding characteristics. Of the acquired data, an addressrelatively poor in data-holding characteristics and unable to beintended for refresh-thinning-out is stored as non-refresh-thinning-outaddress data (D2). Next, refresh-thinning-out fuse cutout logic isdetermined or established according to the distribution of thedata-holding characteristics (S30). This is a process for setting fusecutout to an address poor in data-holding characteristics where memorycells good in data-holding characteristics exist in large numbers, andsetting fuse cutout to an address good in data-holding characteristicswhere memory cells good in data-holding characteristics are few inreverse. The result of logic determination is stored asrefresh-thinning-out fuse cutout logic data (D3).

[0179] A fuse cutting-out process stage will next be explained. Whenfuse cutout is effected on a non-refresh-thinning-out address, based onthe refresh-thinning-out fuse cutout logic data (D3) (S50: YES), dataobtained by adding the redundant address data (D1) and thenon-refresh-thinning-out address data (D2) is loaded as cutout data(S60). When the fuse cutout is not effected on thenon-refresh-thinning-out address (S50: NO), an address obtained bysubtracting the redundant address data (D1) and thenon-refresh-thinning-out address data (D2) from all addresses is loadedas cutout data (S70). The fuse cutout for the refresh-thinning-outcontrol is performed based on the loaded data.

[0180] According to the first specific example of the fifth embodiment,which has been described above, the non-refresh-thinning-out addresspoor in data-holding characteristics and free of the execution of therefresh-thinning-out control, and the redundant address are addedtogether to cut the corresponding fuse in S60. In S70, the redundantaddress and the non-refresh-thinning-out address are subtracted from allthe addresses to thereby perform the fuse cutout. Thus, the setting freeof the execution of thinning-out control can be taken in the redundantregion.

[0181] Since judgment as to whether the refresh operation is executable,is not made to each redundant memory cell subjected to redundancysetting, the test of measuring data-holding characteristics for theredundant memory cell and selecting a predetermined address forperforming refresh-thinning-out control, of redundant addresses asneeded becomes unnecessary. An increase in test time can be suppressed.

[0182] Since the data subjected to redundancy setting is utilized as itis in the redundant region to thereby make it possible to cut out thecorresponding refresh-thinning-out fuse, a control circuit or the likefor avoiding the execution of the refresh-thinning-out control on theredundant region becomes unnecessary.

[0183]FIG. 22 is a second specific example. The present drawing is acircuit block diagram showing a configuration for making a decision asto whether redundancy setting is made to a refresh address Add(C) andthen controlling a refresh-thinning-out control.

[0184] When the refresh address Add(C) is produced, a redundancyjudgment section 51 determines whether redundancy setting is made toeach redundant region 140 i. If the redundancy setting is found to bemade thereto, then the redundancy judgment section 51 outputs aredundant signal REDi and obtains access to the corresponding redundantregion 140 i. Since the redundant region 140 i is generally divided intoa plurality of blocks according to the configuration of thesemiconductor memory device, the redundant signal REDi is also producedfor each divided redundant region 140 i.

[0185] These redundant signals REDi are ORed by an OR logic gate 52 andinputted to a deactivating terminal INH of a refresh-thinning-outcontrol circuit 5 as a redundancy setting signal RED. When theredundancy setting signal RED is inputted to the refresh-thinning-outcontrol circuit 5, the refresh-thinning-out control circuit 5 is broughtinto a non-activation or deactivation state to thereby make it possibleto prohibit thinning-out control. Thus, the setting of avoiding theexecution of the thinning-out control in the redundant region can beperformed.

[0186] According to the second specific example of the fifth embodiment,which has been described above, the prohibition of the thinning-outcontrol in the redundant region can be performed by the correspondingredundant signal REDi outputted from the redundancy judgment section 51and for accessing the corresponding redundant region 140 i. Accordingly,there is no need to effect a specific process on therefresh-thinning-out control by use of redundancy setting data upon acharacteristic test, and a test time can hence be shortened.

[0187]FIG. 23 is a layout conceptual diagram showing column redundancy.Configurations of the column redundancy are set in units divided intoblocks in a row address direction. If such setting is taken, thenrefresh-thinning-out control can be prohibited in predetermined blockunits subjected to column redundancy. While complicated processes suchas the measurement of data-holding characteristics in column redundantregions, etc. are being avoided and the setting of avoiding theexecution of the refresh-thinning-out control in the column redundantregions is being made, the regions can be limited to regions dividedinto blocks. Therefore, a reduction in current consumption by therefresh-thinning-out control can be achieved in regions not subjected tocolumn redundancy setting, and the avoidance of a complicated process inredundancy setting and a reduction in current consumption byrefresh-thinning-out can be rendered compatible with each other uponcolumn redundancy.

[0188] Incidentally, the present invention is not limited to theembodiments referred to above. It is needless to say that variousimprovements and modifications can be made thereto within the scope notdeparting from the substance of the present invention.

[0189] While the first through fifth embodiments have been describedindividually in the present embodiment, for example, it is needless tosay that these configurations or methods can be combined suitably.

[0190] According to the present invention, there can be provided asemiconductor memory device which is capable of achieving a furtherreduction in current consumption insufficient for the conventionalsemiconductor memory device and is free of incurring of an operationalincrease in delay even if applied to a pseudo SRAM or the like havinghigh compatibility and which is capable of realizing a suitablerefresh-thinning-out function to thereby reduce current consumption in astandby state, and a refresh control method of the semiconductor memorydevice.

What is claimed is:
 1. A semiconductor memory device for sequentiallyselecting target word lines according to refresh request signals tothereby perform refresh operations, comprising: a designator section fordesignating a corresponding address group related to a word line groupto be intended for the refresh operation according to a plurality of therefresh request signals; a storage section for storing in advance apredetermined address group related to a predetermined word line groupincluding word lines connected with memory cells having predetermineddata-holding characteristics; a comparator section for comparing thecorresponding address group designated by the designator section and thepredetermined address group stored in the storage section; and ajudgment section for judging whether the refresh operation isexecutable, according to the result of comparison by the comparatorsection.
 2. The semiconductor memory device according to claim 1,wherein the designator section includes a dedicated decoder differentfrom a row address decoder for decoding a corresponding address relatedto each word line intended for the refresh operation.
 3. Thesemiconductor memory device according to claim 1, wherein the designatorsection includes a row address decoder for decoding a correspondingaddress related to each word line intended for the refresh operation. 4.A semiconductor memory device for sequentially selecting target wordlines according to refresh request signals to thereby perform refreshoperations, comprising: a refresh-thinning-out controller sectionincluding a designator section for designating a corresponding addressrelated to a word line intended for the refresh operation according toeach of the refresh request signals, and a judgment section forcomparing the corresponding address and a predetermined address relatedto a predetermined word line connected with one of memory cells eachhaving predetermined data-holding characteristics and judging whetherthe refresh operation is executable, according to the result ofcomparison; and a switching section for switching an active state of therefresh-thinning-out controller section under predetermined conditions;wherein when the refresh-thinning-out controller section isdefunctionalized, the switching section deactivates at least either oneof the designator section or the judgment section.
 5. The semiconductormemory device according to claim 4, wherein the switching sectionincludes a timer section for timing a predetermined time, and the activestate of the refresh-thinning-out controller section is switched foreach predetermined time.
 6. The semiconductor memory device according toclaim 5, wherein the timer section includes a counter section forcounting the number of occurrences of the refresh request signals.
 7. Asemiconductor memory device for sequentially selecting target word linesaccording to refresh request signals to thereby perform refreshoperations, comprising: a storage section for storing each ofpredetermined addresses each compared with a corresponding addressrelated to each word line intended for the refresh operation; a storageswitching section for switching the predetermined addresses to be storedin the storage section between addresses at which memory cells eachhaving first data-holding characteristics are included, and addresses atwhich memory cells each having second data-holding characteristics areincluded, according to a distribution of data-holding characteristicsincluded in memory cells; and a judgment section for switching theresult of judgment as to execution/non-execution of the refreshoperation according to the switching of the storage switching section.8. The semiconductor memory device according to claim 7, wherein thefirst data-holding characteristics are data-holding characteristics sameas or better than predetermined data-holding characteristics, and thesecond data-holding characteristics are data-holding characteristicssame as or poorer than predetermined data-holding characteristics, andthe judgment section reverses the result of judgment as to theexecution/non-execution of the refresh operation between thepredetermined addresses at which memory cells each having the first orsecond data-holding characteristics are included.
 9. A semiconductormemory device for sequentially selecting target word lines according torefresh request signals to thereby perform refresh operations,comprising: a refresh-thinning-out controller section for comparing acorresponding address related to each of the target word lines and eachof predetermined addresses related to predetermined word lines connectedwith memory cells each having predetermined data-holding characteristicsand judging whether the refresh operation is executable, according tothe result of comparison; and an output section activated upon testingand for outputting the result of judgment from the refresh-thinning-outcontroller section to the outside.
 10. The semiconductor memory deviceaccording to claim 9, further including a buffer section for propagatingthe result of judgment to the output section upon the testing.
 11. Thesemiconductor memory device according to claim 9, further including anaddress changer section for switching each of addresses inputted to therefresh-thinning-out controller section to a test address inputted fromoutside as an alternative to the corresponding address upon the testing.12. A semiconductor memory device for sequentially selecting target wordlines according to refresh request signals to thereby perform refreshoperations, comprising: a refresh-thinning-out controller section forcomparing each of corresponding addresses related to each of the targetword lines and each of predetermined addresses related to predeterminedword lines connected with memory cells each having predetermineddata-holding characteristics and judging whether the refresh operationis executable, according to the result of comparison; and redundantmemory cells for relieving defective memory cells; wherein of thecorresponding addresses, redundant addresses in which redundancy settingfor the redundant memory cells has been performed, are not judged by therefresh-thinning-out controller section.
 13. The semiconductor memorydevice according to claim 12, wherein the redundancy setting isperformed with a predetermined number of word lines including theredundant memory cells being as basic units of redundant regions, andthe basic units of the redundant regions are not judged by therefresh-thinning-out controller section.
 14. The semiconductor memorydevice according to claim 13, wherein each of the redundant regions iscolumn redundancy.
 15. The semiconductor memory device according toclaim 12, wherein the refresh-thinning-out controller section includes astorage section for storing in advance predetermined addresses relatedto predetermined word lines connected with memory cells each havingpredetermined data-holding characteristics, and the storage sectionfurther stores the redundant addresses therein.
 16. The semiconductormemory device according to claim 12, further including a redundancyjudgment section for judging whether each of the corresponding addressesis each of the redundant addresses, wherein the refresh-thinning-outcontroller section has a judgment section for determining whether therefresh operation is executable on each of the corresponding addresses,and the judgment section is controlled based on the redundancy judgmentmade by the redundancy judgment section.
 17. A semiconductor memorydevice wherein an external access operation executed based on each ofexternal-access request signals and a refresh operation executed basedon each of refresh request signals produced automatically thereinsideare executed independently of each other, comprising: an arbiter sectionfor making arbitration to the external-access request signal and therefresh request signal; a controller section for controlling decodeprocessing of each corresponding address with respect to either theexternal access operation or the refresh operation determined by thearbiter section; a word line driver section for driving a row addressdecoder for the corresponding address, which is started up by thecontroller section, and each word line selected by the row addressdecoder; and a refresh-thinning-out controller section for making adecision as to execution/non-execution of the refresh operation withrespect to the corresponding address outputted according to the refreshrequest signal; wherein the row address decoder or the word line driversection is activated and controlled based on the result of determinationby the refresh-thinning-out controller section.
 18. A semiconductormemory device wherein an external access operation executed based oneach of external-access request signals and a refresh operation executedbased on each of refresh request signals produced automaticallythereinside are executed independently of each other, comprising: anarbiter section for making arbitration to the external-access requestsignal and the refresh request signal; a refresh request section foroutputting the refresh request signal to the arbiter section; and arefresh-thinning-out controller section for making judgment as toexecution/non-execution of the refresh operation with respect to acorresponding address outputted according to the refresh request signal;wherein the refresh request section is controlled based on the result ofjudgment by the refresh-thinning-out controller section.
 19. A refreshcontrol method of a semiconductor memory device comprising: a step ofsequentially selecting target word lines according to refresh requestsignals to thereby perform refresh operations; and a step of judgingwhether the refresh operation is executable, according to data-holdingcharacteristics stored in memory cells connected to a word line group,for each corresponding address group related to the word line group tobe intended for the refresh operation in response to a plurality of therefresh request signals.
 20. The refresh control method according toclaim 19, wherein the corresponding address group is designated by acorresponding decode address obtained by decoding the correspondingaddress related to each target word line according to the refreshoperation, and the corresponding decode address and predetermined decodeaddresses stored in advance inclusive of word lines connected withmemory cells each having predetermined data-holding characteristics arecompared to thereby discriminate whether the refresh operation isexecutable.
 21. A refresh control method of a semiconductor memorydevice comprising: a step of sequentially selecting target word linesaccording to refresh request signals to thereby perform refreshoperations; and a step of avoiding judgment as toexecution/non-execution of the refresh operation with respect toredundant addresses subject to redundancy setting, of correspondingaddresses related to the target word lines.
 22. The refresh controlmethod according to claim 21, wherein the redundancy setting isperformed with a predetermined number of word lines including redundantmemory cells being as basic units of redundant regions, and the basicunits of the redundant regions are not judged by therefresh-thinning-out controller section.
 23. The refresh control methodaccording to claim 22, wherein the redundancy setting is columnredundancy.
 24. The refresh control method according to claim 21,wherein the redundant addresses are stored in advance together withpredetermined addresses related to predetermined word lines connectedwith memory cells each having predetermined data-holdingcharacteristics.
 25. A refresh control method of a semiconductor memorydevice comprising: a step of executing an external access operationbased on each of external-access request signals and a refresh operationbased on each of refresh request signals produced automaticallythereinside, the external operation and the refresh operation beingexecuted independently of each other; a step of selecting the refreshoperation according to arbitaration to the external-access requestsignal and the refresh request signal and performing a judgment processas to execution/non-execution of the refresh operation relative to thecorresponding address in parallel with a word line driving process madefollowing a decode process of the corresponding address intended for therefresh operation; and a step of activating and controlling the decodeprocess or the word line driving process, based on the result ofjudgment as to the execution/non-execution thereof.
 26. A refreshcontrol method of a semiconductor memory device comprising: an executionstep for executing an external access operation based on each ofexternal-access request signals and a refresh operation based on each ofrefresh request signals produced automatically thereinside, the externaloperation and the refresh operation being executed independently of eachother; an access-operation arbitration step for making arbitration tothe external-access request signal and the refresh request signal; acontrol step for controlling a decode process of each correspondingaddress with respect to either the external access operation or therefresh operation determined by the access-operation arbitration step; arow address decode step started up by the control step and for decodingthe corresponding address; a word line driving step executed followingthe row address decode step; and a refresh-thinning-out control step formaking judgment as to execution/non-execution of the refresh operationrelative to the corresponding address in parallel with the processesfrom the access-operation arbitration step to the word line drivingstep; whereby the row address decode step or the word line driving stepis activated and controlled based on the result of judgment by therefresh-thinning-out control step.
 27. A refresh control method of asemiconductor memory device comprising: a step of executing an externalaccess operation based on each of external-access request signals and arefresh operation based on each of refresh request signals producedautomatically thereinside, the external operation and the refreshoperation being executed independently of each other; a step of judgingwhether the refresh operation is executable, with respect to eachcorresponding address outputted according to the refresh request signal;and a step of arbitrating the refresh request signal and theexternal-access request signal based on the result of judgment.
 28. Arefresh control method of a semiconductor memory device comprising: anexecution step for executing an external access operation based on eachof external-access request signals and a refresh operation based on eachof refresh request signals produced automatically thereinside, theexternal operation and the refresh operation being executedindependently of each other; a refresh-thinning-out control step foreffecting judgment as to execution/non-execution of the refreshoperation on each corresponding address outputted according to therefresh request signal; a refresh request step for allowing the refreshrequest signal to be effective based on the result of judgment by therefresh-thinning-out control step; and an access-operation arbitrationstep for making arbitration to the external-access request signal andthe refresh request signal rendered effective.
 29. A test method of asemiconductor memory device, for performing refresh operations accordingto judgment as to execution/non-execution of the refresh operationsevery refresh request signals while performing redundancy setting,comprising: a redundant address acquiring step for acquiring eachredundant address to be subjected to the redundancy setting; apredetermined address acquiring step for acquiring predeterminedaddresses related to memory cells each having predetermined data-holdingcharacteristics; and a storing step for storing the redundant addressesand the predetermined addresses in the semiconductor memory device inadvance to exclude the two from an object for the judgment as to theexecution/non-execution of the refresh operation.